Power-on reset circuit

ABSTRACT

A power on reset circuit is capable of changing logic level of reset signal at different threshold voltages.

BACKGROUND

1. Field of the Invention

The present invention relates to a power-on reset circuit and, in particular, to a power-on reset circuit capable of changing a logic level of a reset signal at multiple threshold voltages.

2. Description of the Related Art

Most electronic devices have a power-on reset circuit, which is used for outputting a reset signal to logic components of the electronic device. The logic components include, for example, registers, counters and flip-flops, which are sensitive to starting status during boot-up. During periods with power supply inconsistencies, the power-on reset circuit outputs a reset signal to restart the electronic device.

FIG. 1 is a schematic view of a conventional power-on reset circuit 10. The power-on reset circuit 10 includes a pull-up component 12 and a pull-down circuit 14. The pull-up component 12 is a P-MOSFET MP₁ and the pull-down component 14 is an N-MOSFET MN₁.

FIG. 2 is a schematic view of a waveform chart of a reset signal and a threshold voltage of the conventional power-on reset circuit 10 illustrated in FIG. 1. Referring also to FIG. 1, the conductive capability of the P-MOSFET MP₁ is different from the conductive capability of the N-MOSFET MN_(D), so while the voltage level of the power supply V_(DD) is 0V, the P-MOSFET MP₁ is not conducted. Therefore, a voltage, Reset_f, of a capacitor C₁ is 0V and a logic level, Reset, at an output node N₂ of the power-on reset circuit 10 is 0.

While the voltage level of the power supply V_(DD) reaches a threshold voltage V_(RES), the conductive capability of the P-MOSFET is stronger than the capability of the N-MOSFET, so the first logic component X₁ may make a transition for changing an outputted logic level. Meanwhile, a logic level at the output node N₂ of the power-on reset circuit 10 is 1 and the power-on reset circuit 10 may output a reset signal, Reset, having a high logic level to other circuits, not shown, for resetting the circuits in logic level.

When the power supply V_(DD) is closed, voltage of the power supply V_(DD) may begin decreasing. When the voltage level of the power supply V_(DD) is less than the threshold voltage V_(REs), the conductive capability of the P-MOSFET MP₁ is weaker than the conductive capability of the N-MOSFET MN_(D), so the first logic component X₁ may make a transition for changing an outputted logic level. Meanwhile, the logic level at the output node N₂ of the power-on reset circuit 10 may be changed from 1 to 0, so the logic level of the reset signal, Reset, may be 0.

To overcome the disadvantage of the prior art in that the conventional circuit can only change the logic level of the reset signal with respect to a single voltage threshold V_(RES), the present invention provides a power-on reset circuit which is capable of changing logic level of reset signal with respect to multiple threshold voltages.

SUMMARY

In accordance with one embodiment of the present invention, a power-on reset circuit comprises a first pull-up component, a second pull-up component, a first pull-down component, and a first logic component. The first pull-up component is coupled between a power supply and a first node. The second pull-up component is coupled between the power supply and a second node. The first pull-down component is coupled to the first node and a common node, and the first logic component is coupled between the first node and the second node. Moreover, the second pull-up component is actuated based on a voltage at the second node.

In accordance with one embodiment of the present invention, a power-on reset circuit comprises a first pull-up component, a first pull-down component, a second pull-down component, a first logic component, and a second logic component. The first pull-up component is coupled between a power supply and a first node. The first pull-down component is coupled between the first node and the common node. The second pull-down component is coupled between the common node and a third node. The first logic component is coupled between the first node and the second node, and a second logic component is coupled between the second node and the third node. The second pull-down component is actuated based on a voltage at the third node.

In order to provide further understanding of the techniques, means, and effects of the current disclosure, the following detailed description and drawings are hereby presented, such that the purposes, features and aspects of the current disclosure may be thoroughly and concretely appreciated; however, the drawings are provided solely for reference and illustration, without any intention to be used for limiting the current disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The objectives and advantages of the present invention are illustrated with the following description and upon reference to the accompanying drawings in which:

FIG. 1 is a schematic view of a conventional power-on reset circuit;

FIG. 2 is a schematic view of a waveform chart of a reset signal and a threshold voltage of a conventional power-on reset circuit;

FIG. 3 is a schematic view of one embodiment of the present invention showing a power-on reset circuit;

FIG. 4 is a schematic view of one embodiment of the present invention showing a waveform chart of a logic level of reset signal and a voltage level of the power supply of the power-on reset circuit;

FIG. 5 is a schematic view of one embodiment of the present invention indicating a power-on reset circuit; and

FIG. 6 is a schematic view of one embodiment of the present invention indicating a waveform chart of a voltage level of the reset signal and a voltage level of the power supply of a power-on reset circuit.

DETAILED DESCRIPTION OF THE INVENTION

The present invention discloses a power-on reset circuit which is capable of changing logic level of a reset signal at multiple threshold voltages.

FIG. 3 is a schematic view of one embodiment of the present invention showing a power-on reset circuit 30. The power-on reset circuit 30 includes a first pull-up component 32, a second pull-up component 34 and a first pull-down component 36. The first pull-up component 32 is coupled between a power supply V_(DD) and a first node N₁. The second pull-up component 34 is coupled between the power supply V_(DD) and a second node N₂.

The first pull-down component 36 is coupled between the first node N₁ and a common node, which is grounded. A first logic component X₁ is coupled between the first node N₁ and the second node N₂. The second pull-up component 34 is actuated based on a voltage, Reset_fb, at the second node N₂. Moreover, the power-on reset circuit 30 further includes a capacitor C₁, which is coupled between the first node N₁ and the common node.

The first pull-up component 32 is a P-MOSFET MP₁, which has a source connected to the power supply V_(DD), a drain connected to the first node N₁, and a gate connected to the common node. The first pull down component 36 is an N-MOSFET MN_(D), which has a source connected to the common node, a drain connected to the first node N₁, and a gate connected to the power supply V_(DD).

The second pull-up component 34 includes a voltage control component or a P-MOSFET MP₂. The P-MOSFET MP₂ has a source connected to the power supply V_(DD), a drain connected to the first node N₁, and a gate connected to the second node N₂.

FIG. 4 is a schematic view of one embodiment of the present invention showing a waveform chart of a logic level of reset signal and a voltage level of the power supply V_(DD) of the power-on reset circuit 30. Referring also to FIG. 3, when the voltage level of the power supply V_(DD) is 0V, the first pull-up component 32 has not been connected, and a voltage at the first node N₁ is 0V. Meanwhile, a logic level at the second node N₂, Reset_fb, is 0.

When the voltage of the power supply V_(DD) reaches a threshold voltage V₁, a conduction capability of the first pull-up component 32 is stronger than a conduction capability of the first pull-down component 36. Therefore, the voltage at the first node N₁ increases and reaches a high voltage level, so that the first logic component X₁ makes a transition for outputting a logic level 0, the second pull-up component 34 may be conducted, and the power-on reset circuit 30 may output a reset signal to other circuits, not shown, for resetting the circuits in logic level.

While the voltage level of the power supply V_(DD) decreases gradually, the first pull-up component 32 and the second pull-up component 34 are conducted. Therefore, when the voltage level of the power supply V_(DD) decreases and reaches a threshold voltage V_(RES2), the first logic component X₁ makes a transition for outputting a logic level 1 so that the power-on reset circuit 30 may output a reset signal having a low logic level to other circuits, not shown, for resetting the circuits in logic level.

FIG. 5 is a schematic view of one embodiment of the present invention indicating a power-on reset circuit 50. The power-on reset circuit includes a first pull-up component 52, a first pull-down component 54, and a second pull-down component 56. The first pull-up circuit 52 is coupled between a power supply V_(DD) and a first node N₁. The first pull-down component 54 is coupled between the first node N₁ and a common node, which is grounded.

A second pull-down component 56 is coupled between the common node and a third node N₃. A first logic component X₁ is coupled between the first node N₁ and the second node N₂, while a second logic component X₂ is coupled between the second node N₂ and the third node N₃. The second pull-down component 56 is actuated based on a voltage at the third node N₃. The power-on reset circuit further includes a capacitor C₁, which is coupled between the first node N₁ and the common node.

The first pull-up component 52 includes a P-MOSFET MP₁ which has a source coupled to the power supply, a drain coupled to the first node, and a gate coupled to the common node. The first pull-down component includes an N-MOSFET MN_(D), which has a source coupled to the common node, a drain coupled to the first node, and a gate coupled to the power supply.

The second pull-down component 56 includes a voltage control component or an N-MOSFET MN₂. The N-MOSFET MN₂ has a source coupled to the common node, a drain coupled to the first node N₁, and a gate coupled to the third node N₃.

FIG. 6 is a schematic view of one embodiment of the present invention indicating a waveform chart of a voltage level of the reset signal and a voltage level of the power supply V_(DD) of a power-on reset circuit 50. Referring to FIG. 5, when the voltage level of the power supply V_(DD) is 0V, a logic level, Reset_fb, at the second node N2 is 1 and a voltage logic level, Reset, at an output node of the power-on reset circuit 50 is 0.

When the voltage of the power supply V_(DD) reaches a threshold voltage V_(RES3), a conduction capability of the first pull-up component 52 is stronger than a conduction capability of the first pull-down component 54. Therefore, the voltage at the first node N₁ is raised to a high voltage, equal to V_(RES3), by the first pull-up component 52, so that the first logic component X₁ makes a transition for outputting a logic level 0, and the second logic component makes a transition for outputting a logic level 1.

When the logic level of the first logic component X₁ is 0, the logic level, Reset, at the output node is 1 and the voltage logic level, Reset_fb, at the second node N₂ is 0, the power-on reset circuit 50 outputs a reset signal, Reset, having a high logic level to other circuits, not shown, for resetting the circuits in logic level.

As the voltage level of the power supply V_(DD) decreases gradually, the first pull-down component 54 and the second pull-down component 56 are conducted. Therefore, when the voltage level of the power supply V_(DD) decreases and reaches a threshold voltage V₄, the first logic component X₁ and the second logic component X₂ make a transition, and, meanwhile, the threshold voltage V_(RES4) is greater than or equal to the threshold voltage V_(RES3). The power-on reset circuit 50 outputs a reset signal, Reset, having a low logic level to other circuits, not shown, for resetting the circuits in logic level.

Although the present invention and its objectives have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, many of the processes discussed above can be implemented using different methodologies, replaced by other processes, or a combination thereof.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. 

1. A power-on reset circuit, comprising: a first pull-up component, coupled between a power supply and a first node; a second pull-up component, coupled between the power supply and a second node; a first pull-down component, coupled to the first node and a common node; and a first logic component, coupled between the first node and the second node, wherein the second pull-up component is actuated based on a voltage at the second node.
 2. The power-on reset circuit of claim 1, wherein the first pull-up component includes a P-MOSFET, which has a source connected to the power supply, a drain connected to the first node, and a gate connected to the common node, wherein the first pull-down includes an N-MOSFET, which has a source connected to the common node, a drain connected to the first node, and a gate connected to the power supply.
 3. The power-on reset circuit of claim 1, wherein the second pull-up component includes a P-MOSFET or a voltage control component.
 4. The power-on reset circuit of claim 2, wherein the P-MOSFET has a source connected to the power supply, a drain connected to the first node, and a gate connected to the second node.
 5. The power-on reset circuit of claim 1, further comprising a capacitor coupled between the first node and the common node.
 6. A power-on reset circuit, comprising: a first pull-up component, coupled between a power supply and a first node; a first pull-down component, coupled between the first node and the common node; a second pull-down component, coupled between the common node and a third node; a first logic component, coupled between the first node and the second node; and a second logic component, coupled between the second node and the third node, wherein the second pull-down component is actuated based on a voltage at the third node.
 7. The power-on reset circuit of claim 6, wherein the first pull-up component includes a P-MOSFET, which has a source connected to the power supply, a drain connected to the first node, and a gate connected to the common node, wherein the first pull-down includes an N-MOSFET, which has a source connected to the common node, a drain connected to the first node, and a gate connected to the power supply.
 8. The power-on reset circuit of claim 6, wherein the second pull-up component includes an N-MOSFET or a voltage control component.
 9. The power-on reset circuit of claim 8, wherein the N-MOSFET has a source connected to the common node, a drain connected to the first node, and a gate connected to the third node.
 10. The power-on reset circuit of claim 6, further comprising a capacitor coupled between the first node and the common node. 